Altera JESD204B IP - Manual (Page 89)

that the input data is valid. The checker flags an error when it finds any single mismatch between the
expected data and input data.
Ramp Wave Checker
The ramp wave checker is implemented in the same way as in the ramp wave generator. To do a
comparison, an initial seed internally generates a set of expected data pattern result to XOR'ed with the
input data. The seed is updated only when the enable signal is active, which indicates that the input data is
valid. The checker flags an error when it finds any single mismatch between the expected data and input
data.
Transport Layer
The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at
the RX path.
The transport layer provides the following services to the application layer (AL) and the DLL:
• The assembler at the TX path:
• maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of
non-scrambled octets, before streaming them to the DLL.
• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface
during TX data streaming.
• The deassembler at the RX path:
• maps the descrambled octets from the DLL to a specific conversion sample format before streaming
them to the AL (through the Avalon-ST interface).
• reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface
during RX data streaming.
Supported System Configuration
The transport layer supports static configurations where before compilation, you can modify the configu‐
rations using the IP core's parameter editor in the Quartus II software. To change to another configura‐
tion, you have to recompile the design. The following list describes the supported configurations for the
transport layer:
• Data rate (maximum) = 12.5 Gbps (
F1_FRAMECLK_DIV
= 4 and
F2_FRAMECLK_DIV
= 2)
• L = 1–8
• F = 1, 2, 4, 8
• N = 12, 13, 14, 15, 16
• N' = 16
• CS = 0–3
• CF = 0
• HD = 0 (for F=2, 4, 8), 1 (for F=1)
Dynamic Downscaling Of System Parameters (L, N, and F)
The Dynamic Downscaling of System Parameters (DDSP) feature enables you to dynamically downscale
specific JESD204B system parameters through the CSR, without having to recompile the FPGA.
The transport layer supports dynamic downscaling of parameters L, F, and N only. The supported M and
S parameters are determined by the L, F, and N' parameters. Some parameters (for example, CS and N')
5-8 Ramp Wave Checker
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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