Altera JESD204B IP - Manual (Page 59)

The Altera PLL IP core should provide both the frame clock and link clock from the same PLL as these
two clocks are treated as synchronous in the design.
For Subclass 0 mode, the device clock is not required to sample the SYSREF signal edge. The link clock
does not need to be phase compensated to capture SYSREF. Therefore, you can generate both the link
clock and frame clock using direct mode in the Altera PLL IP core. If F = 4, where link clock is the same as
the frame clock, you can use the parallel clock output from the transceiver (
txphy_clk
or
rxphy_clk
signal).
Related Information
Clock Correlation on page 4-23
Local Multi-Frame Clock
The Local Multi-Frame Clock (LMFC) is a counter generated from the link clock and depends on the F
and K parameter.
The K parameter must be set between 1 to 32 and meet the requirement of at least a minimum of 17 octets
and a maximum of 1024 octets in a single multi-frame. In a 32-bit architecture, the K × F must also be in
the order of four.
In a Subclass 1 deterministic latency system, the SYSREF frequency is distributed to the devices to align
them in the system. The SYSREF resets the internal LMFC clock edge when the sampled SYSREF signal's
rising edge transition from 0 to 1. Due to source synchronous signaling of SYSREF with respect to the
device clock sampling (provided from the clock chip), the JESD204 IP core does not directly use the
device clock to sample SYSREF but instead uses the link clock to sample SYSREF. Therefore, the Altera
PLL IP core that provides the link clock must to be in normal mode to phase-compensate the link clock
to the device clock.
Based on hardware testing, to get a fixed latency, at least 32 octets are recommended in an LMFC period
so that there is a margin to tune the RBD release opportunity to compensate any lane-to-lane deskew
across multiple resets. If F = 1, then K = 32 would be optimal as it provides enough margin for system
latency variation. If F = 2, then K = 16 and above (18/20/22/24/26/28/30/32) is sufficient to compensate
lane-to-lane deskew.
The JESD204B IP core implements the local multi-frame clock as a counter that increments in link clock
counts. The local multi-frame clock counter is equal to (F × K/4) in link clock as units. The rising edge of
SYSREF resets the local multi-frame clock counter to 0. There are two CSR bits that controls SYSREF
sampling.
•
csr_sysref_singledet
—resets the local multi-frame clock counter once and automatically cleared
after SYSREF is sampled. This register also prevents CGS exit to bypass SYSREF sampling.
•
csr_sysref_alwayson
—resets the local multi-frame clock counter at every rising edge of SYSREF that
it detects. This register also enables the SYSREF period checker. If the provided SYSREF period violates
the F and K parameter, an interrupt is triggered. However, this register does not prevent CGS-SYSREF
race condition.
The following conditions occur if both CSR bits are set:
• resets the local multi-frame clock counter at every rising edge of SYSREF.
• prevents CGS-SYSREF race condition.
• checks SYSREF period.
4-22 Local Multi-Frame Clock
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Functional Description
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