Altera JESD204B IP - Manual (Page 150)

Check these items:
• Review the schematic and board layout file to determine the polarity of the physical pin connection.
• Use assignment editor and pin planner to check the pin assignment and I/O standard for each pin.
• Use RTL viewer in the Quartus II software to verify that the top level port are connected to the lower
level module that you instantiate.
Debugging JESD204B Link Using SignalTap II and System Console
The SignalTap II provides dynamic view of signals while the system console provides access to the
JESD204B IP core register sets through the Avalon-MM interfaces.
The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues.
To use the system console, your design must contain a Qsys subsystem with the JTAG-to-Avalon-MM
Master bridge component and the Merlin slave translator ports that connect to the JESD204B IP core
Avalon-MM interface.
PHY Layer
Verify the RX PHY status through these signals in the <ip_variant_name>.v:
• rx_is_lockedtodata
• rx_analogreset
• rx_digitalreset
• rx_cal_busy
Verify the TX PHY status through these signals in the <ip_variant_name>.v:
• pll_locked
• pll_powerdown
• tx_analogreset
• tx_digitalreset
• tx_cal_busy
Verify the RX_TX PHY status through these signals in the <ip_variant_name>.v:
• rx_is_lockedtodata
• rx_analogreset
• rx_digitalreset
• rx_cal_busy
• rx_seriallpbken
• pll_locked
• pll_powerdown
• tx_analogreset
• tx_digitalreset
• tx_cal_busy
Use the
rxphy_clk[0]
or
txphy_clk[0]
signal as sampling clock for the SignalTap II.
For a normal operation of the JESD204B RX path, the
rx_is_lockedtodata
bit for each lane should be
"1" while the
rx_cal_busy
,
rx_analogreset
, and
rx_digitalreset
bit for each lane should be "0".
For a normal operation of the JESD204B TX path, the
pll_locked
bit for each lane should be "1" while
the
tx_cal_busy
,
pll_powerdown
,
tx_analogreset
, and
tx_digitalreset
bit for each lane should be
"0".
UG-01142
2015.05.04
Debugging JESD204B Link Using SignalTap II and System Console 7-3
JESD204B IP Core Debug Guidelines Altera Corporation
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