Altera JESD204B IP - Manual (Page 2)

Contents
JESD204B IP Core Quick Reference................................................................... 1-1
About the JESD204B IP Core..............................................................................2-1
Datapath Modes........................................................................................................................................... 2-3
IP Core Variation.........................................................................................................................................2-3
JESD204B IP Core Configuration..............................................................................................................2-4
Run-Time Configuration................................................................................................................2-4
Channel Bonding......................................................................................................................................... 2-5
Performance and Resource Utilization.....................................................................................................2-6
Getting Started.................................................................................................... 3-1
Introduction to Altera IP Cores.................................................................................................................3-1
Installing and Licensing IP Cores..............................................................................................................3-2
Upgrading IP Cores.....................................................................................................................................3-2
IP Catalog and Parameter Editor...............................................................................................................3-5
Design Walkthrough................................................................................................................................... 3-6
Creating a New Quartus II Project................................................................................................ 3-6
Parameterizing and Generating the IP Core................................................................................3-7
Generating and Simulating the IP Core Testbench.................................................................... 3-8
Compiling the JESD204B IP Core Design..................................................................................3-10
Programming an FPGA Device................................................................................................... 3-11
JESD204B IP Core Design Considerations............................................................................................ 3-11
Integrating the JESD204B IP core in Qsys................................................................................. 3-11
Pin Assignments.............................................................................................................................3-12
Adding External Transceiver PLL............................................................................................... 3-13
Timing Constraints For Input Clocks.........................................................................................3-13
JESD204B IP Core Parameters.................................................................................................................3-16
JESD204B IP Core Component Files...................................................................................................... 3-21
JESD204B IP Core Testbench.................................................................................................................. 3-21
Testbench Simulation Flow..........................................................................................................3-23
JESD204B IP Core Functional Description........................................................4-1
Transmitter................................................................................................................................................... 4-4
TX Data Link Layer..........................................................................................................................4-5
TX PHY Layer.................................................................................................................................. 4-8
Receiver......................................................................................................................................................... 4-8
RX Data Link Layer..........................................................................................................................4-9
RX PHY Layer................................................................................................................................ 4-12
Operation.................................................................................................................................................... 4-13
Operating Modes........................................................................................................................... 4-13
TOC-2 JESD204B IP Core User Guide
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