Altera JESD204B IP - Manual (Page 66)

Signal Width Direction Description
reconfig_to_xcvr[] • (L+1)*70 if
bonding mode =
"xN"
• L*140 if
bonding mode =
feedback
compensation
Input Reconfiguration signals from the Transceiver
Reconfiguration Controller IP core to the PHY
device.
This signal is only applicable for V series
FPGA variants.
You must connect these signals to the
Transceiver Reconfiguration Controller IP
core regardless of whether run-time reconfigu‐
ration is enabled or disabled. The Transceiver
Reconfiguration Controller IP core also
supports various calibration function during
transceiver power up.
reconfig_from_xcvr[] • (L+1)*46 if
bonding mode =
"xN"
• L*92 if bonding
mode =
feedback
compensation
Output Reconfiguration signals to the Transceiver
Reconfiguration Controller IP core.
This signal is only applicable for V series
FPGA variants.
You must connect these signals to the
Transceiver Reconfiguration Controller IP
core regardless of whether run-time reconfigu‐
ration is enabled or disabled. The Transceiver
Reconfiguration Controller IP core also
supports various calibration function during
transceiver power up.
reconfig_clk 1 Input The Avalon-MM clock input. The frequency
range is 100–125 MHz.
This signal is only available if you enable
dynamic reconfiguration for Arria 10 FPGA
variants.
reconfig_reset 1 Input Reset signal for the Transceiver Reconfigura‐
tion Controller IP core. This signal is active
high and level sensitive.
This signal is only available if you enable
dynamic reconfiguration for Arria 10 FPGA
variants.
reconfig_avmm_
address[]
log
2
L*1024 Input
The Avalon-MM address.
This signal is only available if you enable
dynamic reconfiguration for Arria 10 FPGA
variants.
UG-01142
2015.05.04
Transmitter 4-29
JESD204B IP Core Functional Description Altera Corporation
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