Altera JESD204B IP User Manual
Page 115
F = 2
F2_
FRAMCL
K_DIV=1
1st frameclk
cnt=0:
jesd204_rx_
dataout[63:0] =
{F12F13,
F8F9,F4F5, F0F1}
Case1: M=1, S=4
M0S0=F0F1, M0S1=F4F5,
M0S2=F8F9, M0S3=F12F13
Case2: M=2, S=2
M0S0=F0F1, M0S1=F4F5,
M1S0=F8F9, M1S1=F12F13
Case3: M=4, S=1
M0S0=F0F1, M1S0=F4F5,
M2S0=F8F9, M3S0=F12F13
2nd frameclk
cnt=1:
jesd204_rx_
dataout[63:0] =
{F14F15,
F10F11,F6F7, F2F3}
Case1: M=1, S=4
M0S0=F2F3, M0S1=F6F7,
M0S2=F10F11,
M0S3=F14F15
Case2: M=2, S=2
M0S0=F2F3, M0S1=F6F7,
M1S0=F10F11,
M1S1=F14F15
Case3: M=4, S=1
M0S0=F2F3, M1S0=F6F7,
M2S0=F10F11,
M3S0=F14F15
F2_
FRAMCL
K_DIV=2
jesd204_rx_dataout[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}
Table 5-15: Data Mapping for F=4, L=4
F = 4
Lane
L3
L2
L1
L0
Data In
{F12, F13, F14,
F15}
{F8, F9, F10, F11} {F4, F5, F6, F7}
{F0, F1, F2, F3}
Supported M
and S
M*S=8 for F=4, L=4
F=4 supports either (case1: M=1, S=8), (case2: M=2, S=4), (case3: M=4, S=2) or (case4:
M=8, S=1)
F=4
jesd204_rx_
dataout[127:0] =
{F14F15,
F12F13,F10F11,
F8F9,F6F7,F4F5,
F2F3,F0F1}
Case1: M=1, S=8
{M0S7, M0S6, M0S5, M0S4, M0S3, M0S2,
M0S1, M0S0}
Case2: M=2, S=4
{M1S3, M1S2, M1S1, M1S0, M0S3, M0S2,
M0S1, M0S0}
Case3: M=4, S=2
{M3S1, M3S0, M2S1, M2S0, M1S1, M1S0,
M0S1, M0S0}
Case4: M=8, S=1
{M7S0, M6S0, M5S0, M4S0, M3S0, M2S0,
M1S0, M0S0}
5-34
RX Path Data Remapping
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines