Adding external transceiver pll, Timing constraints for input clocks, Adding external transceiver pll -13 – Altera JESD204B IP User Manual
Page 27: Timing constraints for input clocks -13
Adding External Transceiver PLL
The JESD204B IP core variations that target an Arria 10 FPGA device require external transceiver PLLs
for compilation.
JESD204B IP core variations that target a V-series FPGA device contain transceiver PLLs. Therefore, no
external PLLs are required for compilation.
You are recommend to use an ATX PLL or CMU PLL to get a better jitter performance.
Note: The PMA width is 20 bits for Hard PCS and 40 bits for Soft PCS.
Related Information
More information about the Arria 10 transceiver PLLs and clock network.
Timing Constraints For Input Clocks
When you generate the JESD204B IP core variation, the Quartus II software generates a Synopsys Design
Constraints File (
.sdc
) that specifies the timing constraints for the input clocks to your IP core.
When you generate the JESD204B IP core, your design is not yet complete and the JESD204B IP core is
not yet connected in the design. The final clock names and paths are not yet known. Therefore, the
Quartus II software cannot incorporate the final signal names in the
.sdc
file that it automatically
generates. Instead, you must manually modify the clock signal names in this file to integrate these
constraints with the timing constraints for your full design.
This section describes how to integrate the timing constraints that the Quartus II software generates with
your IP core into the timing constraints for your design.
The Quartus II software automatically generates the
altera_jesd204.sdc
file that contains the JESD204B IP
core's timing constraints.
Three clocks are created at the input clock port:
• JESD204B TX IP core:
•
txlink_clk
•
reconfig_to_xcvr[0]
(for Arria V, Cyclone V, and Stratix V devices only)
•
reconfig_clk
(for Arria 10 device only)
•
tx_avs_clk
• JESD204B RX IP core:
•
rxlink_clk
•
reconfig_to_xcvr[0]
(for Arria V, Cyclone V, and Stratix V devices only)
•
reconfig_clk
(for Arria 10 device only)
•
rx_avs_clk
In a functional system design, these clocks (except for
reconfig_to_xcvr[0]
clock) are typically
provided by the core PLL.
UG-01142
2015.05.04
Adding External Transceiver PLL
3-13
Getting Started
Altera Corporation