Altera JESD204B IP - Manual (Page 60)

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Clock Correlation on page 4-23
Clock Correlation
This section describes the clock correlation between the device clock, link clock, frame clock, and local
multi-frame clock.
Example 1
Targeted device with LMF=222, K=16 and Data rate = 6.5 Gbps
Device Clock selected = 325 MHz (obtained during IP core generation)
Link Clock = 6.5 GHz/40 = 162.5 MHz Frame Clock = 6.5 GHz/(10x2) = 325 MHz
Local Multi-frame clock = 325 MHz / 16 = 20.3125 MHz
SYSREF Frequency = Local Multi-frame Clock / n; (n = integer; 1, 2, …)
Local multi-frame clock counter = (F × K/4) = (2×16/4) = 8 link clocks
(18)
Example 2
Targeted device with LMF=244, K=16 and Data rate = 5.0 Gbps
Device Clock selected = 125 MHz (obtained during IP core generation)
Link Clock = 5 GHz/40 = 125 MHz
(19)
Frame Clock = 5 GHz /(10×4) = 125 MHz (19)
Local Multi-frame clock = 125 MHz / 16 = 7.8125 MHz
SYSREF Frequency = Local Multi-frame Clock / n; (n = integer; 1, 2, …)
Local multi-frame clock counter = (F × K/4) = (4×8/4) = 8 link clocks
(18)
Example 3
Targeted device with LMF=421, K=32 and Data rate = 10.0 Gbps
Device Clock selected = 250 MHz (obtained during IP core generation)
Link Clock = 10 GHz/40 = 250 MHz
Frame Clock = 10 GHz/(10×1) = 1 GHz
(20)
Local Multi-frame clock = 1 GHz / 32 = 31.25 MHz
SYSREF Frequency = Local Multi-frame Clock / n; (n = integer; 1, 2, …)
Local multi-frame clock counter = (F × K/4) = (1×32/4) = 8 link clocks
(18)
(18) Eight link clocks means that the local multi-frame clock counts from value 0 to 7 and then loopback to 0.
(19) The link clock and frame clock are running at the same frequency. You only need to generate one clock from
the Altera PLL or Altera IO PLL IP core.
(20) For this example, the frame clock may not be able to run up to 1 GHz in the FPGA fabric. The JESD204B
transport layer in the design example supports running the data stream of half rate (1 GHz/2 = 500 MHz), at
two times the data bus width or of quarter rate (1GHz/4 = 250MHz), at four times the data bus width.
UG-01142
2015.05.04
Clock Correlation 4-23
JESD204B IP Core Functional Description Altera Corporation
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