Altera JESD204B IP - Manual (Page 3)

Scrambler/Descrambler................................................................................................................ 4-14
SYNC_N Signal..............................................................................................................................4-14
Link Reinitialization...................................................................................................................... 4-16
Link Startup Sequence...................................................................................................................4-17
Error Reporting Through SYNC_N Signal................................................................................ 4-18
Clocking Scheme........................................................................................................................................4-18
Device Clock...................................................................................................................................4-20
Link Clock.......................................................................................................................................4-21
Local Multi-Frame Clock..............................................................................................................4-22
Clock Correlation...........................................................................................................................4-23
Reset Scheme.............................................................................................................................................. 4-24
Reset Sequence............................................................................................................................... 4-25
Signals..........................................................................................................................................................4-26
Transmitter..................................................................................................................................... 4-27
Receiver........................................................................................................................................... 4-36
Registers...................................................................................................................................................... 4-43
Register Access Type Convention............................................................................................... 4-43
JESD204B IP Core Design Guidelines................................................................ 5-1
JESD204B IP Core Design Example..........................................................................................................5-1
Design Example Components........................................................................................................5-3
System Parameters.........................................................................................................................5-40
System Interface Signals................................................................................................................5-44
Example Feature: Dynamic Reconfiguration.............................................................................5-49
Generating and Simulating the Design Example.......................................................................5-55
Generating the Design Example For Compilation....................................................................5-56
Compiling the JESD204B IP Core Design Example................................................................. 5-57
JESD204B IP Core Deterministic Latency Implementation Guidelines........... 6-1
Constraining Incoming SYSREF Signal....................................................................................................6-1
Programmable RBD Offset.........................................................................................................................6-2
Programmable LMFC Offset......................................................................................................................6-5
JESD204B IP Core Debug Guidelines.................................................................7-1
Clocking Scheme..........................................................................................................................................7-1
JESD204B Parameters................................................................................................................................. 7-1
SPI Programming.........................................................................................................................................7-2
Converter and FPGA Operating Conditions........................................................................................... 7-2
Signal Polarity and FPGA Pin Assignment..............................................................................................7-2
Debugging JESD204B Link Using SignalTap II and System Console.................................................. 7-3
Additional Information...................................................................................... 8-1
JESD204B IP Core Document Revision History..................................................................................... 8-1
How to Contact Altera................................................................................................................................ 8-3
JESD204B IP Core User Guide TOC-3
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