Altera JESD204B IP - Manual (Page 58)

Figure 4-8: JESD204B Subsystem Clock Diagram (For Arria V and Stratix V Devices)
Clock Jitter Cleaner
Converter Device 2
Converter Device
device_clock SYSREF
Trace Matching (1)
MAC PHY
Transceiver
PLL (2)
JESD204B IP Core
L
SYNC_N
Core PLL
FPGA Device
(Normal Mode) (3)
JESD204B
Transport
Layer
Avalon-ST
Link Clock
Frame Clock avs_clock
Test
Pattern
Generator/
Checker
Trace Matching (1)
SYSREF
FPGA Device
Clock
Notes:
1. The device clock to the Altera core PLL and SYSREF must be trace matched. The device clock to the converter device and SYSREF must be
trace matched. The phase offset between the SYSREF to the FPGA and converter devices should be minimal.
2. For Arria 10 devices, the transceiver PLL is outside of the JESD204B IP core. For Arria V and Stratix V devices, the transceiver PLL is part of the JESD204B IP core.
3. The Altera core PLL provdes the link clock, frame clock, and AVS clock. The link clock and frame clock must be synchronous.
Related Information
Clock Correlation on page 4-23
Link Clock
The device clock is the timing reference for the JESD204B system.
Due to the clock network architecture in the FPGA, JESD204 IP core does not use the device clock to
clock the SYSREF signal because the GCLK or RCLK is not fully compensated. You are recommended to
use the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IP core (in Arria 10 devices)
to generate both the link clock and frame clock. The Altera PLL IP core must operate in normal mode or
source synchronous mode to achieve the following state:
• the GCLK and RCLK clock network latency is fully compensated.
• the link clock and frame clock at the registers are phase-aligned to the input of the clock pin.
To provide consistency across the design regardless of frame clock and sampling clock, the link clock is
used as a timing reference.
UG-01142
2015.05.04
Link Clock 4-21
JESD204B IP Core Functional Description Altera Corporation
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