Pin assignments, Pin assignments -12 – Altera JESD204B IP User Manual
Page 26
Figure 3-4: Example of Connecting JESD204B IP Core with Other Qsys Components in Qsys
Figure shows an example of how you can connect the IP core with other Qsys components in Qsys.
Related Information
on page 5-8
Pin Assignments
Set the pin assignments before you compile to provide direction to the Quartus II software Fitter tool. You
must also specify the signals that should be assigned to device I/O pins.
You can create virtual pins to avoid making specific pin assignments for top-level signals. This is useful
when you want to perform compilation, but are not ready to map the design to hardware. Altera
recommends that you create virtual pins for all unused top-level signals to improve timing closure.
Note: Do not create virtual pins for the clock or reset signals.
3-12
Pin Assignments
UG-01142
2015.05.04
Altera Corporation
Getting Started