Performance and resource utilization, Performance and resource utilization -6 – Altera JESD204B IP User Manual
Page 11
Device Family
Core Variation
Bonding Mode Configuration
Maximum Number of
Lanes (L)
Arria V GZ
Arria 10
Stratix V
PHY only
Bonded
32
(2)
Non-bonded
32
(2)
MAC and PHY
Bonded
8
Non-bonded
8
Performance and Resource Utilization
Table 2-3: JESD204B IP Core FPGA Performance
Device Family
PMA Speed
Grade
FPGA Fabric
Speed Grade
Data Rate
Link Clock F
MAX
(MHz)
Enable Hard
PCS (Gbps)
Enable Soft PCS
(Gbps)
(3)
Cyclone V
5
<Any
supported
speed grade>
1.0 to 5.0
—
125.00
Cyclone V
6
6 or 7
1.0 to 3.125
—
78.125
Arria V
<Any
supported
speed grade>
<Any
supported
speed grade>
1.0 to 6.55
—
(4)
163.84
Arria V GZ
2
3
2.0 to 9.9
—
(4)
247.50
Arria V GZ
3
4
2.0 to 8.8
—
(4)
220.00
Arria 10
1
1
2.0 to 12.0
2.0 to 12.5
312.50
Arria 10
2
1
2.0 to 12.0
2.0 to 12.5
312.50
Arria 10
2
2
2.0 to 9.83
2.0 to 12.5
312.50
Arria 10
3
1
2.0 to 12.0
2.0 to 12.5
312.50
Arria 10
3
2
2.0 to 9.83
2.0 to 12.5
—
Arria 10
4
3
2.0 to 8.83
2.0 to 12.5
312.50
Arria 10
5
3
2.0 to 8.0
2.0 to 8.0
312.50
Stratix V
1
1 or 2
2.0 to 12.2
2.0 to 12.5
312.50
Stratix V
2
1 or 2
2.0 to 12.2
2.0 to 12.5
312.50
Stratix V
2
3
2.0 to 9.8
2.0 to 12.5
(5)
312.50
(3)
Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an
additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional
10–20% increase in resource utilization.
(4)
Enabling Soft PCS does not increase the data rate for the device family and speed grade. You are
recommended to select the Enable Hard PCS option.
2-6
Performance and Resource Utilization
UG-01142
2015.05.04
Altera Corporation
About the JESD204B IP Core