Altera JESD204B IP - Manual (Page 139)

JESD204B IP Core Deterministic Latency
Implementation Guidelines
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2015.05.04
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Subclass 1 and Subclass 2 modes support deterministic latency. This section describes the features
available in the JESD204B IP core that you can use to achieve Subclass 1 deterministic latency in your
design. This section also covers some best practices for Subclass 1 implementation like constraining the
incoming SYSREF signal.
Features available:
• Programmable RBD offset.
• Programmable LMFC offset.
Constraining Incoming SYSREF Signal
The SYSREF signal resets the LMFC counter in the IP core for subclass 1 implementation. Constraining
the SYSREF signal ensures that the setup relationship between SYSREF and device clock is established.
The setup time is analyzed when you set the timing constraint for the SYSREF signal in the user
.sdc file.
When the setup time is met, the SYSREF signal detection by the IP core is deterministic; the number of
link clock cycles of SYSREF signal that arrives at the FPGA pin to the LMFC counter resets, is determin‐
istic.
Apply the
set_input_delay
constraint on the SYSREF signal with respect to device clock in the user .sdc
file:
set_input_delay -clock <device clock name at FPGA pin> <sysref IO delay in ns>
[get_ports <sysref name at FPGA pin >]
The SYSREF IO delay is the board trace length mismatch between device clock and SYSREF. For example:
set_input_delay -clock device_clk 0.5 [get_ports sysref]
The above statement constrains the FPGA SYSREF signal (sysref), with respect to the FPGA device clock
(device_clk) pin. The trace length mismatch resulted in 500 ps or 0.5 ns difference in time arrival at the
FPGA pins between SYSREF and device clock.
In most cases, the register in the IP core, which detects the SYSREF signal, is far away from the SYSREF
I/O pin. The long interconnect routing delay results in timing violation. You are recommeded to use
multi-stages pipeline registers to close timing. Use the same clock domain as the JESD204B IP core's
rxlink_clk
and
txlink_clk
to clock the multi-stages pipeline registers.
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