Altera JESD204B IP - Manual (Page 82)

JESD204B IP Core Design Guidelines
5
2015.05.04
UG-01142 Subscribe
Send Feedback
This section describes the design example included with the IP core and some implementation guidelines.
JESD204B IP Core Design Example
The design example entity consists of various components that interface with the JESD204B IP core to
demonstrate the following features:
• single or multiple link configuration
• different LMF settings with scrambling and internal serial loopback enabled
• interoperability against diverse converter devices
• dynamic reconfiguration
You can use the synthesizable design example entity in both simulation and hardware environments.
Figure 5-1 illustrates the high level system architecture of the JESD204B IP core design example.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134