About the jesd204b ip core, About the jesd204b ip core -1 – Altera JESD204B IP User Manual

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About the JESD204B IP Core

2

2015.05.04

UG-01142

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The Altera JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or

analog-to-digital (ADC) converters to transfer data to FPGA devices. This unidirectional serial interface

runs at a maximum data rate of 12.5 Gbps. This protocol offers higher bandwidth, low I/O count and

supports scalability in both number of lanes and data rates. The JESD204B IP core addresses multi-device

synchronization by introducing Subclass 1 and Subclass 2 to achieve deterministic latency.
The JESD204B IP core incorporates:
• Media access control (MAC)—data link layer (DLL) block that controls the link states and character

replacement.

• Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.
The JESD204B IP core does not incorporate the Transport Layer (TL) that controls the frame assembly

and disassembly. The TL and test components are provided as part of a design example component where

you can customize the design for different converter devices.

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