Jesd204b ip core functional description, Jesd204b ip core functional description -1 – Altera JESD204B IP User Manual
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JESD204B IP Core Functional Description
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The JESD204B IP core implements a transmitter (TX) and receiver (RX) block. Each block has two layers
and consists of the following components:
• Media access control (MAC)—DLL block that consists of the link layer (link state machine and
character replacement), CSR, Subclass 1 and 2 deterministic latency, scrambler or descrambler, and
multiframe counter.
• Physical layer (PHY)—PCS and PMA block that consists of the 8B/10B encoder, word aligner,
serializer, and deserializer.
You can specify the datapath and wrapper for your design and generate them separately.
The TX and RX blocks in the DLL utilizes the Avalon-ST interface to transmit or receive data and the
Avalon-MM interface to access the CSRs. The TX and RX blocks operate on 32-bit data width per
channel, where the frame assembly packs the data into four octets per channel. Multiple TX and RX
blocks can share the clock and reset if the link rates are the same.
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