NEC PD750008 - Manual (Page 10)

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CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 21
3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21
3.1.1 Data Memory Bank Structure .................................................................... 21
3.1.2 Data Memory Addressing Modes .............................................................. 23
3.2 GENERAL REGISTER BANK CONFIGURATION ................................................. 34
3.3 MEMORY-MAPPED I/O .......................................................................................... 39
CHAPTER 4 INTERNAL CPU FUNCTIONS ......................................................................................... 45
4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS ................................................... 45
4.1.1 Differences between Mk I Mode and Mk II Mode ..................................... 45
4.1.2 Setting of the Stack Bank Selection Register (SBS) ................................ 46
4.2 PROGRAM COUNTER (PC) ................................................................................. 47
4.3 PROGRAM MEMORY (ROM) ................................................................................ 48
4.4 DATA MEMORY (RAM) .......................................................................................... 53
4.4.1 Data Memory Configuration....................................................................... 53
4.4.2 Specification of a Data Memory Bank ....................................................... 54
4.5 GENERAL REGISTER ............................................................................................ 56
4.6 ACCUMULATOR ..................................................................................................... 57
4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ............ 58
4.8 PROGRAM STATUS WORD (PSW) ...................................................................... 62
4.9 BANK SELECT REGISTER (BS) ........................................................................... 65
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ...................................................................... 67
5.1 DIGITAL I/O PORTS ............................................................................................. 67
5.1.1 Types, Features, and Configurations of Digital I/O Ports ........................ 68
5.1.2 I/O Mode Setting ........................................................................................ 74
5.1.3 Digital I/O Port Manipulation Instructions ................................................. 76
5.1.4 Digital I/O Port Operation .......................................................................... 79
5.1.5 Specification of Bilt-in Pull-Up Resistors .................................................. 81
5.1.6 I/O Timing of Digital I/O Ports ................................................................... 82
5.2 CLOCK GENERATOR ............................................................................................ 84
5.2.1 Clock Generator Configuration .................................................................. 84
5.2.2 Functions and Operations of the Clock Generator ................................... 85
5.2.3 System Clock and CPU Clock Setting ...................................................... 94
5.2.4 Clock Output Circuit ................................................................................... 96
5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER ................................................... 99
5.3.1 Configuration of the Basic Interval Timer/Watchdog Timer ..................... 99
5.3.2 Basic Interval Timer Mode Register (BTM) .............................................. 99
5.3.3 Watchdog Timer Enable Flag (WDTM) ..................................................... 101
5.3.4 Operation of the Basic Interval Timer ....................................................... 101