NEC PD750008 - Manual (Page 136)

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µPD750008 USER'S MANUAL
Figure 5-33. Timer/Event Counter Mode Register Setup (2/2)
(b) In the case of timer counter (channel 1)
(b) Timer/event counter output enable flag (TOEn)
The TOEn is manipulated by a bit manipulation instruction.
The TOEn is cleared to 0 by an internal reset signal.
Figure 5-34. Timer/Event Counter Output Enable Flag Setup
Timer start indication bit
When “1” is written to the bit, the counter and IRQT1 flag are cleared.
If bit 2 is set to “1”, count operation is started.
TM13
TM12
Operation mode
Count operation
Other than above
0
1
Stop (retention of count contents)
Count operation
7 6
TM16
5
TM15
4
TM14
3
TM13
2
TM12
1 0 Address
FA8H
Symbol
TM1
Count pulse (CP) selection bit
f X /2 12
f X /2 10
f X /2 8
f
X
/2 6
Not to be set
TM15
0
0
1
1
TM16
1
1
1
1
TM14
0
1
0
1
Count pulse (CP)
Address
FA2H
FAAH
TOE0
TOE1
Channel 0
Channel 1
0
1
Disabled (outputs the low-level signal).
Enabled.
Timer/event counter output enable flag (W)