NEC PD750008 - Manual (Page 49)

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CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
(5) 8-bit register indirect addressing (@HL)
In this addressing mode, the data pointer (HL register pair) indirectly specifies any area in the data memory
space in units of eight bits.
The 4-bit data at the address determined with bit 0 of the data pointer (bit 0 of the L register) set to 0 and
the 4-bit data at the address incremented by 1 are processed as a pair on an 8-bit basis with the 8-bit
accumulator (XA register pair).
A memory bank is specified in the same way as the 4-bit register indirect addressing with the HL register
specified. In this case, MB = MBE·MBS.
This addressing mode can be applied to the MOV, XCH, and SKE instructions.
Examples 1. A comparison is made to determine whether the value of the count register (T0) of timer/
event counter 0 is equal to the data at addresses 30H and 31H.
DATA EQU 30H
CLR1 MBE
MOV HL,#DATA
MOV XA,T0 ; XA <– Count register 0
SKE XA,@HL ; XA = (HL)?
2. The data memory of 00H to FFH is cleared to 0.
CLR1 RBE
CLR1 MBE
MOV XA,#00H
MOV HL,#04H
LOOP: MOV @HL,XA ; (HL) <– XA
INCS HL
INCS HL
BR LOOP
(6) Bit manipulation addressing
This addressing mode is used to perform bit manipulations (such as Boolean operations and bit transfer)
for each bit in the data memory space.
The 1-bit direct addressing mode can be applied only to the set, reset, and test instructions. On the other
hand, the bit manipulation addressing enables a wide variety of bit manipulations such as Boolean
operations using the AND1, OR1, and XOR1 instructions, bit transfers using the MOV1 instruction, and
test and reset operations using the SKTCLR instruction.
There are three types of bit manipulation addressing. The user can choose from these options according
to the data memory address used.