NEC PD750008 - Manual (Page 247)

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CHAPTER 8 RESET FUNCTION
Table 8-1. Statuses of the Hardware after a Reset (2/2)
Processor clock control register
(PCC)
System clock control register
(SCC)
Clock output mode register
(CLOM)
Interrupt request flag (IRQxxx)
Interrupt enable flag (IExxx)
Priority selection register (IPS)
INT0, INT1 and INT2 mode
registers (IM0, IM1, IM2)
Output buffer
Output latch
I/O mode registers (PMGA,
PMGB, PMGC)
Pull-up resistor specification
register (POGA, POGB)
Hardware
Generation of a RESET
signal during operation
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Undefined
Sub-oscillator control register (SOS)
Clock
generator,
clock
output
circuit
Interrupt
Digital
ports
Generation of a RESET
signal in a standby mode
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Held Bit sequential buffers (BSB0 to BSB3)