NEC PD750008 - Manual (Page 43)

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CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
3.1.2 Data Memory Addressing Modes
With the architecture of the µPD750008, seven addressing modes summarized in Figures 3-2 and 3-3, and
Table 3-1 are available to address data memory space efficiently for each bit length of data to be processed.
These addressing modes enable more efficient programming.
(1) 1-bit direct addressing (mem.bit)
In this addressing mode, the operand of an instruction can directly specify any bit in the entire data memory
space.
A particular memory bank (MB) is always used in this addressing mode. In the MBE = 0 mode, when an
address from 00H to 7FH is specified in the operand, memory bank 0 (MB = 0) is always used. When
an address from 80H to FFH is specified, memory bank 15 (MB = 15) is always used. Accordingly, both
the data area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH
can be addressed in the MBE = 0 mode.
In the MBE = 1 mode, MB = MBS, and specifiable data memory space can be expanded.
This addressing mode can be applied to four instructions: bit set and reset instructions (SET1 and CLR1),
and bit test instructions (SKT and SKF).
Example FLAG1 is set, FLAG2 is reset, and whether FLAG3 is zero is tested.
FLAG1 EQU 03FH.1 ; Bit 1 at address 3FH
FLAG2 EQU 087H.2 ; Bit 2 at address 87H
FLAG3 EQU 0A7H.0 ; Bit 0 at address A7H
SET1 MBE ; MBE <– 1
SEL MB0 ; MBS <– 0
SET1 FLAG1 ; FLAG1 <– 1
CLR1 FLAG2 ; FLAG2 <– 0
SKF FLAG3 ; FLAG3 = 0?