NEC PD750008 - Manual (Page 102)

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µPD750008 USER'S MANUAL
Figure 5-8. Pull-Up Resistor Specification Register Format
Pull-up resistor specification register group A
Pull-up resistor specification register group B
5.1.6 I/O Timing of Digital I/O Ports
Figure 5-9 shows the timing of data output to an output latch and the timing of taking in pin data or output
latch data on the internal bus.
Figure 5-10 shows an ON timing chart when a built-in pull-up resistor is connected to a port pin by software.
Figure 5-9. I/O Timing Chart of Digital I/O Ports (1/2)
(a) When data is input by a 1-machine cycle instruction
PO7 PO6 — — PO3 PO1 PO2 PO0
7 6 5 4 3 1 2 0
FDCH
Address
POGA
Symbol
Port 0 (P01 - P03)
Port 1 (P10 - P13)
Port 2 (P20 - P23)
Port 3 (P30 - P33)
Port 6 (P60 - P63)
Port 7 (P70 - P73)
0
1
Built-in pull-up resistor not connected
Built-in pull-up resistor connected
Specification contents
— — —
7 6 5 4 3 1 2 0
FDEH
Address
POGB
Symbol
Port 8 (P80, P81)
— — — — PO8
Instruction
execution
1 machine cycle
Manipulation instruction
Input timing