NEC PD750008 - Manual (Page 154)

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µPD750008 USER'S MANUAL
(3) Shift register (SIO)
Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which
performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock.
Serial transfer is started by writing data to SIO.
In transmission, data written to SIO is output on the serial output (SO) or serial data bus (SB0 or SB1).
In receive operation, data is read from the serial input (SI) or SB0 or SB1 into SIO.
Data can be read from or written to SIO by using an 8-bit manipulation instruction.
When the RESET signal is generated during operation, the value of SIO is undefined. When the RESET
signal is generated in the standby mode, the value of SIO is preserved.
Shift operation is stopped after 8-bit send or receive operation is completed.
Figure 5-42. Peripheral Hardware of Shift Register
The timing for reading SIO and start of serial transfer (writing to SIO) is as follows:
• When the serial interface operation enable/disable bit (CSIE) = 1. However, the case where CSIE
is set to 1 after data is written to the shift register is excluded.
• When the serial clock is masked after 8-bit serial transfer
• SCK is high.
When reading from or writing to SIO, make sure that SCK is high.
In the two-wire serial I/O mode and SBI mode, the pins specified for the data bus are used for both input
and output. Because the configuration of output pins is N-ch open-drain, write FFH in SIO for devices
that are to receive data.
(4) Slave address register (SVA)
The slave address register (SVA) is an 8-bit register for a slave to set its slave address (number assigned
to it).
SVA is manipulated using an 8-bit manipulation instruction.
When the RESET signal is generated, the value of SVA is undefined. However, the value of SVA is
preserved when the RESET signal is generated in the standby mode.
SVA has the following two functions:
D Q
SET CLR
RELT
CMDT
CLK
BUSY/ACK
Internal bus
Address
comparator
Shift register
SO latch
Shift clock
N-ch open-drain output
CSIM