NEC PD750008 - Manual (Page 180)

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µPD750008 USER'S MANUAL
Bus release trigger bit (W)
RELT Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or
after serial transfer.
(4) Serial clock selection
To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial
clock can be selected out of the following four clocks:
Table 5-9. Serial Clock Selection and Application (In the SBI Mode)
Mode register Serial clock
Timing for shift register R/W and
Application CSIM CSIM
Source
Masking of
start of serial transfer
1 0 serial clock
0 0 External Automatically <1> In the operation halt mode Slave CPU
SCK masked when (CSIE = 0)
0 1 TOUT
8-bit data <2> When the serial clock is
Arbitrary-speed
flip-flop
transfer is masked after 8-bit transfer
serial transfer
completed <3> When SCK is high
1 0 f
X
/2 4 Middle-speed
serial transfer
1 1 f
X
/2 3 High-speed
serial transfer
When the internal system clock is selected, SCK is internally terminated when the 8th clock has been
output, and is externally counted until the slave enters the ready state.
(5) Signals
Figures 5-60 to 5-65 show signals to be generated in the SBI mode and flag operations on the SBIC. Table
5-10 lists signals used in the SBI mode.