NEC PD750008 - Manual (Page 138)

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µPD750008 USER'S MANUAL
(3) Timer/event counter operation
The timer/event counter operates as follows.
Figure 5-35 shows the configuration of the timer/event counter.
<1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register
(Tn).
<2> The Tn is compared with the modulo register (TMODn), and if they are equal, a match signal is
generated and the interrupt request flag (IRQTn) is set. At the same time, the timer out flip-flop (TOUT
flip-flop) is inverted.
Figure 5-36 is a timing chart of the timer/event counter.
The timer/event counter normally begins operation in the following procedure.
<1> Set a count in the TMODn.
<2> Set the operating mode, count pulse, and start indication in the TMn.
Caution Set a value other than 00H in the modulo register (TMODn).
When using the timer/event counter output pin (PTOn), set the dual function pin P2n as follows.
<1> Clear the output latch of P2n.
<2> Set port 2 to the output mode.
<3> Make a status wherein the internal pull-up resistor is not connected in port 2.
<4> Set the timer/event counter output enable flag (TOEn) to 1.
Figure 5-35. Configuration of Timer/Event Counter
Note Channel 0 of the timer/event counter only.
Modulo register (TMODn)
Comparator
Count register (Tn)
Match
Clear
TOUT flip-flop
To serial interface Note
PTOn
INTTn
(IRQTn set signal)
MPX
CP
TI0 Note
Internal
clock
TOUT0