NEC PD750008 - Manual (Page 214)

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µPD750008 USER'S MANUAL
(4) Interrupt status flags
The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of
processing currently executed by the CPU.
By using the content of these flags, the interrupt priority control circuit controls multiple interrupts as
indicated in Table 6-3.
A 4-bit manipulation instruction or bit manipulation instruction can be used to set and reset IST0 and IST1,
so that multiple interrupts are enabled by changing the current status of execution. IST0 and IST1 can
be manipulated on a single-bit basis at any time regardless of MBE setting.
Before IST0 or IST1 is manipulated, the DI instruction must be executed to disable interrupts, then the
EI instruction must be executed to enable interrupts.
IST1 and IST0 as well as the other PSW bits are saved in the stack memory when an interrupt is accepted
and the status of IST0 and IST1 changes to a status one level higher. When a RETI instruction is executed,
the former values of IST1 and IST0 are resumed.
Inputting a RESET signal clears the content of the flag to 0.
Table 6-3. Interrupt Processing Statuses of IST0 and IST1
IST1 IST0
Processing
CPU operation
Interrupts that
After acceptance
status can be accepted IST1 IST0
0 0 Status 0 Is processing the normal program. All 0 1
0 1 Status 1 Is processing a low- or high-order Only high-order 1 0
interrupt. interrupts
1 0 Status 2 Is processing a high-order interrupt. No — —
1 1 Not to be set