NEC PD750008 - Manual (Page 134)

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µPD750008 USER'S MANUAL
(2) Timer/event counter output enable flag (TOE0, TOE1)
The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0
and PTO1 pins in the timer out flip-flop (TOUT flip-flop ) status.
The timer out flip-flop is inverted by the match signal sent from the comparator. When bit 3 of the timer/
event counter mode register (TM0, TM1) is set to 1, the timer out flip-flop is cleared to 0.
TOE0, TOE1, and timer out flip-flop are cleared to 0 by a RESET signal generation.
Figure 5-32. Timer/Event Counter Output Enable Flag Format
5.5.2 8-bit timer/event counter mode operation
It is used as an 8-bit timer/event counter in this mode. It performs an 8-bit programmable interval timer
and event counter operation (channel 0 only).
(1) Register setting
The following three registers and one flag are used in the 8-bit timer/event counter mode.
• Timer/event counter mode register (TMn)
• Timer/event counter count register (Tn)
• Timer/event counter modulo register (TMODn)
• Timer/event counter output enable flag (TOEn)
(a) Timer/event counter mode register (TMn)
When the 8-bit timer/event counter mode is used, TMn must be set as shown in Figure 5-33 (For the
format of the TMn, see Figures 5-30 and 5-31).
The TMn is manipulated by an 8-bit manipulation instruction. Bit 3 is a timer start indication bit and
can be manipulated bit-wise and is automatically cleared to 0 when the timer starts.
The TMn is cleared to 00H when an internal reset signal is generated.
Address
FA2H
FAAH
TOE0
TOE1
Channel 0
Channel 1
0
1
Disabled.
Enabled.
Timer/event counter output enable flag (W)