NEC PD750008 - Manual (Page 84)

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µPD750008 USER'S MANUAL
Table 4-5. Information Indicated by the Interrupt Status Flag
IST1 IST0 Status of processing Processing and interrupt control being performed
0 0 Status 0 Normal program processing is being performed.
Any interrupts are acceptable.
0 1 Status 1 A lower- or higher-priority interrupt is being serviced.
Higher-priority interrupts are acceptable.
1 0 Status 2 A higher-priority interrupt is being serviced.
No interrupts are acceptable.
1 1 — Not to be set
The interrupt priority control circuit (Figure 6-1) checks this flag to control multiple interrupts.
The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted,
then are automatically set to a one-step higher status. The RETI instruction restores the contents present
before an interrupt occurs.
The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of
processing being performed can be changed by program control.
Caution The user must always disable interrupts with the DI instruction before manipulating this
flag, and must enable interrupts with the EI instruction after manipulating this flag.
(4) Memory bank enable flag (MBE)
The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for
the high-order four bits of a 12-bit data memory address.
The MBE can be set or reset any time with a bit manipulation instruction, regardless of memory bank
setting.
When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space
to be addressed.
When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See
Figure 3-2.)
A RESET signal automatically initializes the MBE by setting the MBE to the content of bit 7 at program
memory address 0.
In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address
table for servicing the interrupt.
Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.
(5) Register bank enable flag (RBE)
The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank
configuration.
The RBE can be set or reset any time with a bit manipulation instruction, regardless of memory bank
setting.
When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending
on the setting of the register bank select register (RBS).