NEC PD750008 User Manual
Page 14
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LIST OF FIGURES (1/4)
Figure No.
Title
Page
2-1
Pin Input/Output Circuits ..................................................................................................
18
3-1
Use of MBE = 0 Mode and MBE = 1 Mode .....................................................................
22
3-2
Data Memory Organization and Addressing Range of Each Addressing Mode ............
24
3-3
Updating Static RAM Addresses ......................................................................................
28
3-4
Example of Register Bank Selection ...............................................................................
35
3-5
General Register Configuration (4-bit Processing) .........................................................
37
3-6
General Register Configuration (8-bit Processing) .........................................................
38
3-7
µPD750008 I/O Map .........................................................................................................
40
4-1
Stack Bank Selection Register Format ............................................................................
46
4-2
Program Counter Organization ........................................................................................
47
4-3
Program Memory Map (in µPD750004) ...........................................................................
49
4-4
Program Memory Map (in µPD750006) ...........................................................................
50
4-5
Program Memory Map (in µPD750008) ...........................................................................
51
4-6
Program Memory Map (in µPD75P0016).........................................................................
52
4-7
Data Memory Map ............................................................................................................
54
4-8
General Register Format ..................................................................................................
56
4-9
Register Pair Format ........................................................................................................
57
4-10
Accumulator ......................................................................................................................
57
4-11
Format of Stack Pointer and Stack Bank Select Register ..............................................
59
4-12
Data Saved to the Stack Memory (Mk I Mode) ...............................................................
59
4-13
Data Restored from the Stack Memory (Mk I Mode) ......................................................
60
4-14
Data Saved to the Stack Memory (Mk II Mode) ..............................................................
60
4-15
Data Restored from the Stack Memory (Mk II Mode) .....................................................
61
4-16
Program Status Word Format ..........................................................................................
62
4-17
Bank Select Register Format ...........................................................................................
65
5-1
Data Memory Addresses of Digital Ports .........................................................................
67
5-2
Configurations of Ports 0 and 1 .......................................................................................
69
5-3
Configurations of Ports 2 and 7 .......................................................................................
70
5-4
Configurations of Ports 3n and 6n (n = 0 to 3) ................................................................
71
5-5
Configurations of Ports 4 and 5 .......................................................................................
72
5-6
Configuration of Port 8 .....................................................................................................
73
5-7
Formats of Port Mode Registers ......................................................................................
75
5-8
Pull-Up Resistor Specification Register Format ..............................................................
82