NEC PD750008 - Manual (Page 176)

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µPD750008 USER'S MANUAL
SB0, SB1
8 9
ACK BUSY READY
SCK
(f) Busy signal (BUSY) and ready signal (READY)
The busy signal informs the master that a slave is getting ready for data transfer.
The ready signal informs the master that a slave is ready for data transfer.
Figure 5-59. Busy and Ready Signals
In the SBI mode, a slave notifies the master of the busy state by changing SB0 (or SB1) from high
to low.
The busy signal is output following the acknowledge signal output by the master or a slave. The busy
signal is set and released in phase with the falling edge of SCK. The master automatically terminates
output of serial clock SCK when the busy signal is released.
The master can transfer the next data when the busy signal is released and a slave enters the state
in which the ready signal is to be output.
(3) Register setting
To set the SBI mode, manipulate the following two registers:
• Serial operation mode register (CSIM)
• Serial bus interface control register (SBIC)
(a) Serial operation mode register (CSIM)
To use the SBI mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section
5.6.3.)
CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be
manipulated bit by bit.
When the RESET signal is input, CSIM is set to 00H.
In the figure below, hatched portions indicate the bits used in the SBI mode.
Remark (R): Read only
(W): Write only
CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
FE0H
CSIM
7 6 5 4 3 2 1 0
Address
Serial clock selection bit (W)
Serial interface operation mode selection
bit (W)
Wake-up function specification bit (W)
Match signal from address comparator (R)
Serial interface operation enable/disable specification bit (W)