NEC PD750008 - Manual (Page 57)

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CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
Figure 3-5. General Register Configuration (4-bit Processing)
X
H
D
B
X
H
D
B
X
H
D
B
X
H
D
B
01H
03H
05H
07H
09H
0BH
0DH
0FH
11H
13H
15H
17H
19H
1BH
1DH
1FH
A
L
E
C
A
L
E
C
A
L
E
C
A
L
E
C
00H
02H
04H
06H
08H
0AH
0CH
0EH
10H
12H
14H
16H
18H
1AH
1CH
1EH
Register bank 0
(RBE·RBS = 0)
Register bank 1
(RBE·RBS = 1)
Register bank 2
(RBE·RBS = 2)
Register bank 3
(RBE·RBS = 3)