NEC PD750008 - Manual (Page 94)

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µPD750008 USER'S MANUAL
5.1.2 I/O Mode Setting
The I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O modes
of ports 3 and 6 can be set bit by bit by port mode register group A (PMGA). The I/O modes of ports 2, 4,
5, and 7 can be set in units of four bits by port mode register group B (PMGB). The I/O mode of port 8 can
be set in units of two bits by port mode register group C (PMGC).
Each port functions as an input port when the corresponding bit of the port mode register is set to 0, and
functions as an output port when the same corresponding bit is set to 1.
When the output mode is selected by the port mode register, the contents of the output latch appear on
the output pins, and so the contents of the output latch must be changed to a desired value before the output
mode is set.
An 8-bit memory manipulation instruction is used to set port mode register group A, B, or C.
A RESET signal clears all bits of each port mode register to 0. This means that the output buffers are set
off, and all ports are placed in the input mode.
Example P30, P31, P62, and P63 are used as input pins, and P32, P33, P60, and P61 are used as output
pins.
CLR1 MBE ; or SEL MB15
MOV XA,#3CH
MOV PMGA,XA