NEC PD750008 - Manual (Page 137)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(2) Timer/event counter time setting
[Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP)
frequency] selected by setting the mode register.
n+1
T (sec) = = (n + 1) · (resolution)
f
CP
T (sec) : Timer setup time (seconds)
f
CP
(Hz) : Count pulse frequency (Hz)
n : Modulo register content (n • 0)
Once the timer is set, interrupt request signal (IRQTn) is generated at the intervals set in the timer.
Table 5-6 lists the resolution and longest setup time (time when FFH is set in the modulo register) for each
count pulse to the timer/event counter.
Table 5-6. Resolution and Longest Setup Time
(a) When timer/event counter (channel 0)
Mode register At 6.00 MHz At 4.19 MHz
TM06 TM05 TM04 Resolution Longest setup time Resolution Longest setup time
1 0 0 171 µs 43.7 ms 244 µs 62.5 ms
1 0 1 42.7 µs 10.9 ms 61.0 µs 15.6 ms
1 1 0 10.7 µs 2.73 ms 15.3 µs 3.91 ms
1 1 1 2.67 µs 683 µs 3.82 µs 977 µs
(b) When timer counter (channel 1)
Mode register At 6.00 MHz At 4.19 MHz
TM16 TM15 TM14 Resolution Longest setup time Resolution Longest setup time
1 0 0 685 µs 175 ms 980 µs 250 ms
1 0 1 171 µs 43.7 ms 244 µs 62.5 ms
1 1 0 42.7 µs 10.9 ms 61.0 µs 15.6 ms
1 1 1 10.7 µs 2.73 ms 15.3 µs 3.91 ms