NEC PD750008 - Manual (Page 140)

120
µPD750008 USER'S MANUAL
<Sample program>
SEL MB15
MOV XA,#100 – 1
MOV TMOD0,XA ; Set the modulo register
MOV XA,#00001100B
MOV TM0,XA ; Set the mode register
EI
EI IET0 ; Enable INTT0
5.5.3 Notes on Timer/Event Counter Applications
(1) Time error at the start of the timer
A maximum error of one count pulse (CP) cycle from a value calculated according to Section 5.5.2 (2)
occurs in a time period from the start of the timer (bit 3 of the TM0 is set) to the generation of a match
signal. This is because the count register T0 is cleared not in phase with the CP as shown in Figure
5-37.
Figure 5-37. Error at the Start of the Timer
(2) Notes on the start of the timer
Usually, when the timer is started (bit 3 of the TM0 is set), the count register T0 and the interrupt request
flag (IRQT0) are cleared. However, when the timer is placed in the operation mode, and the setting of
IRQT0 and the start of the timer occur at the same time, IRQT0 may not be cleared. This causes no problem
if IRQT0 is used for a vectored interrupt. However, if IRQT0 is being tested, a problem arises because
IRQT0 is set even if the timer is started. Accordingly, in a situation where the timer is started on such
timing that IRQT0 may be set, the timer must be restarted after it is once stopped (bit 2 of the TM0 is cleared
to 0), or timer start operation must be performed twice.
Example The timer is started on such timing that IRQT0 may be set.
SEL MB15
MOV XA,#0
MOV TM0,XA ; Stop the timer
MOV XA,#4CH
MOV TM0,XA ; Restart
or
SEL MB15
SET1 TM0.3
SET1 TM0.3 ; Restart
CP
Count register
Timer start Timer start
0 1 2 3 0 1 2