NEC PD750008 - Manual (Page 135)

115
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Figure 5-33. Timer/Event Counter Mode Register Setup (1/2)
(a) In the case of timer/event counter (channel 0)
Timer start indication bit
When “1” is written into the bit, the counter and IRQT0 flag are cleared.
If bit 2 is set to “1”, count operation is started.
TM03
TM02
Operation mode
Count operation
0
1
Stop (retention of count contents)
Count operation
7 6
TM06
5
TM05
4
TM04
3
TM03
2
TM02
1 0 Address
FA0H
Symbol
TM0
Count pulse (CP) selection bit
TI0 rising edge
TI0 falling edge
f X /2 10
f
X
/2 8
f X /2 6
f X /2 4
Not to be set
TM05
0
0
0
0
1
1
TM06
0
0
1
1
1
1
TM04
0
1
0
1
0
1
Count pulse (CP)
Other than above