NEC PD750008 - Manual (Page 34)

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µPD750008 USER'S MANUAL
2.2.6 PCL: Output Pin Used Also for Port 2
This is the programmable clock output pin. It is used to supply the clock pulse to a peripheral LSI circuit
such as a slave microcomputer or A/D converter.
A RESET signal clears the clock mode register (CLOM) to 0, disabling clock output, then the pin is placed
in the normal mode to function as a normal port.
2.2.7 BUZ: Output Pin Used Also for Port 2
An arbitrary frequency (2.048, 4.096, or 32.768 kHz) output on this pin can be used for sounding the buzzer
or trimming the system clock frequency. This pin is used also as the P23 pin, and can be used only when
bit 7 (WM.7) of the clock mode register (WM) is set to 1.
A RESET signal places this pin in the normal operation mode as a general port (see Section 5.4.2 for
details).
2.2.8 SCK, SO/SB0, SI/SB1: Tristate I/O Pins Used Also as Port 0
These are I/O pins for serial interface. They operate according to the setting of the serial operation mode
registers (CSIM).
A RESET signal stops serial interface operation and places these pins in the input port mode.
A Schmitt-triggered input is used for each pin.
2.2.9 INT4: Input Pin Used Also as Port 0
INT4 is an external vectored interrupt input pin, which is rising edge active as well as falling edge active.
When a signal applied to this pin goes from low to high or from high to low, the interrupt request flag is set.
INT4 is an asynchronous input, and can accept a signal with some high level width or low level width
regardless of what the CPU clock is.
The INT4 pin can also be used to release the STOP and HALT modes. A Schmitt-triggered input is used
for this pin.
2.2.10 INT0, INT1: Input Pins Used Also for Port 1
These are edge detection vectored interrupt input pins. INT0 has a noise eliminator. The edge to be
detected can be selected using the edge detection mode registers (IM0, IM1).
(1) INT0 (bits 0 and 1 of IM0)
(a) Rising edge active
(b) Falling edge active
(c) Both rising and falling edges active
(d) External interrupt signal input disabled
(2) INT1 (bit 0 of IM1)
(a) Rising edge active
(b) Falling edge active