NEC PD750008 - Manual (Page 236)

216
µPD750008 USER'S MANUAL
7.1 SETTING OF STANDBY MODES AND OPERATION STATUS
Table 7-1. Operation Statuses in the Standby Mode
Notes 1. Operation is possible only when the main system clock operates.
2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection
mode register (IM0) (when IM02 = 1).
A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.
(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.)
STOP instruction or HALT instruction must always be followed by an NOP instruction.
When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from
the time when PCC is rewritten as shown in Table 5-5 to the time when the CPU clock signal is changed.
When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby
mode is released, it is necessary to rewrite PCC and set the standby mode after as many machine cycles
as required to change the CPU clock pulse have elapsed.
In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,
including general registers, flags, mode registers, and output latches, are retained.
Caution 1. When the STOP mode is set, the X1 input is internally connected to V
SS
(ground
potential) to suppress leakage at the crystal oscillator circuitry. This means that the
STOP mode cannot be used with a system that uses an external clock.
Instruction for setting
System clock for setting
Clock oscillator
Basic interval
timer/watchdog
timer
Serial interface
Timer/event
counter
Timer counter
Clock timer
External interrupt
CPU
Release signal
HALT mode
HALT instruction
Can be set either with the main
system clock or the subsystem clock
Only the CPU clock F stops its
operation (oscillation continues)
Can operate only at main system
clock oscillation. (IRQBT is set at
reference time intervals.)
Can operate only when external SCK
input is selected as the serial clock or
at main system clock oscillation.
Can operate only when TI0 pin input
is specified as the count clock or at
main system clock oscillation.
Can operate Note 1
Can operate
STOP mode
STOP instruction
Can be set only when operating on
the main system clock
Only the main system clock stops its
operation
Does not operate
Can operate only when the external
SCK input is selected for the serial
clock
Can operate only when the TI0 pin
input is selected for the count clock
Does not operate
Can operate when f
XT
is selected as
the count clock
INT1, INT2, and INT4 can operate.
Only INT0 cannot operate.
Note 2
Does not operate
Operation
status
Item
An interrupt request signal from hardware whose operation is enabled by the
interrupt enable flag or the generation of a RESET signal
Mode