NEC PD750008 - Manual (Page 106)

86
µPD750008 USER'S MANUAL
(1) Processor clock control register (PCC)
The PCC is a 4-bit register for selecting a CPU clock F with the low-order two bits and for controlling the
CPU operation mode with the high-order two bits (see Figure 5-12).
When bit 3 or bit 2 is set to 1, the standby mode is set. When the standby mode is released by the standby
release signal, these bits are automatically cleared to return to the normal operation mode. (See Chapter
7 for details.)
A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order
two bits are set to 0.)
Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively.
The STOP instruction and HALT instruction can always be executed regardless of MBE setting.
The CPU clock can be selected only while the processor is operated by the main system clock. When
the processor is operated by the subsystem clock, the low-order 2 bits of the PCC are invalidated, and
f
XT
/4 is automatically set. The STOP instruction can be executed only when the processor is operated
by the main system clock.
Examples 1. The machine cycle is entered in highest-speed mode (0.67 µs at f
X
= 6.00 MHz).
SEL MB15
MOV A,#0011B
MOV PCC,A
2. The machine cycle is set to 1.91 µs (at f
X
= 4.19 MHz).
SEL MB15
MOV A,#0010B
MOV PCC,A
3. The STOP mode is set. (A STOP instruction or HALT instruction must always be followed
by an NOP instruction.)
STOP
NOP
A RESET signal clears the PCC to 0.