NEC PD750008 - Manual (Page 61)

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CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP
Figure 3-7. µPD750008 I/O Map (2/5)
Notes 1. TOE0: Timer/event counter output enable flag (W)
2. TOE1: Timer counter output enable flag (W)
FA0H
FA2H
FA4H
FA6H
FA8H
FACH
Address
b3 b2 b1 b0
Hardware name (symbol)
R/ W
1 bit 4 bits 8 bits
Remarks
Number of bits that can be
manipulated
Bit
manipulation
addressing
Timer/event counter mode register (TM0)
Timer/event counter modulo register (TMOD0) R/ W – – –
–
– –
mem.bit
–
TOE0 Note 1 W – – mem.bit
Timer/event counter count register (T0) R – – –
FAAH TOE1 Note 2 W – – mem.bit
R/ W Timer counter mode register (TM1)
–
– –
mem.bit
–
Timer counter count register (T1) R – – –
FAEH
Timer counter modulo register (TMOD1) R/W – – –
Bit write manipu-
lation is enabled
only for bit 3.
Bit write manipu-
lation is enabled
only for bit 3.
R/ W
(W)
(R/W)
(W)
(R/W)