NEC PD750008 - Manual (Page 62)

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µPD750008 USER'S MANUAL
Figure 3-7. µPD750008 I/O Map (3/5)
Remarks 1. IExxx : Interrupt enable flag
2. IRQxxx : Interrupt request flag
Notes 1. Only bit 3 can be manipulated by an EI/DI instruction.
2. Bits 3 and 2 can be manipulated bit by bit by a STOP/HALT instruction.
(R/ W)
FB0H
FB2H
FB3H
FB4H
FB5H
FB7H
FB8H
FBCH
FBDH
FC0H
FC2H
Address
b3 b2 b1 b0
Hardware name (symbol)
R/ W
1 bit 4 bits 8 bits
Remarks
Number of bits that can be
manipulated
R/ W
–
–
Note 1
Bit
manipulation
addressing
INT0 edge detection mode register (IM0)
Manipulation in
8-bit units is
enabled only
for reading.
R/ W
R/ W
R/ W
R/ W
(R)
–
fmem.bit
–
Bit sequential buffer 3 (BSB3)
–
IST1
Program status word (PSW)
CY
(R)
(R/ W)
–
–
R/ W
R/ W
fmem.bit
Interrupt priority select register (IPS)
Processor clock control register (PCC)
INT1 edge detection mode register (IM1)
Bits 3, 2, and 1
are fixed to 0.
R/ W – –
FB6H INT2 edge detection mode register (IM2)
Bits 3 and 2 are
fixed to 0.
R/ W
Bits 2 and 1 are
fixed to 0.
FBAH
R/ W
R/ W
–
–
–
FBEH
FBFH
R/ W
R/ W
–
–
–
IST0
SK2
MBE
SK1
RBE
SK0
IE4
IET1
IE1
IRQ4
IRQT1
IRQ1
IEBT
IET0
IE0
IRQBT
IRQT0
IRQ0
IECSI
IEW
IE2
IRQCSI
IRQW
IRQ2
FC1H
FC3H
R/ W
R/ W
R/ W
R/ W
Bit sequential buffer 2 (BSB2)
Bit sequential buffer 1 (BSB1)
Bit sequential buffer 0 (BSB0)
mem.bit
pmem.@L
System clock control register (SCC)
Note 2
(R/W)
–
FCFH R/ W Sub-oscillator control register (SOS) – – –