NEC PD750008 - Manual (Page 188)

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µPD750008 USER'S MANUAL
(7) Address match detection method
In the SBI mode, communication starts when the master selects a particular slave device by outputting
an address.
An address match is detected by hardware. The slave address register (SVA) is available. In the wake-
up state (WUP = 1), IRQCSI is set only when the address transmitted by the master and the value held
in SVA match.
Cautions 1. Whether a slave is selected is determined by detecting a match for a slave ad-
dress received after bus release (in the state of RELD = 1).
An address match is detected usually using an address match interrupt (IRQCSI)
generated when WUP is set to 1. So detect selection/nonselection state by slave
address when WUP is set to 1.
2. When determining whether a slave is selected without using an interrupt when
WUP is 0, do not use the address match detection method. Instead, use transfer
of commands set in advance in a program.
(8) Error detection
In the SBI mode, the state of serial bus SB0 (or SB1) being used for communication is loaded into the
shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods
described below.
(a) Comparing SIO data before start of transmission with SIO data after start of transmission
With this method, the occurrence of a transmission error is assumed if two SIO values disagree with
each other.
(b) Using the slave address register (SVA)
Transmit data is set in SIO and SVA as well before the data is transmitted. On completion of
transmission, the COI bit (match signal from the address comparator) of serial operation mode register
(CSIM) is tested. If the result is 1, the transmission is regarded as successful. If the result is 0, the
occurrence of a transmission error is assumed.
(9) Communication operation
In the SBI mode, the master usually selects a slave device to communicate with from multiple devices
by outputting the address of the slave to the serial bus.
After selecting a device to communicate with, the master exchanges commands and data with the slave
device, thus establishing serial communication.
Figures 5-67 to 5-70 show the timing charts of data communication operations.
In the SBI mode, the shift register performs shift operation on the falling edge of the serial clock (SCK).
Transmit data is held on the SO latch, and is output on the SB0/P02 or SB1/P03 pin starting with the MSB.
Receive data applied to the SB0 (or SB1) pin is latched in the shift register on the rising edge of SCK.