NEC PD750008 - Manual (Page 235)

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CHAPTER 7 STANDBY FUNCTION
CHAPTER 7 STANDBY FUNCTION
The µPD750008 provides a standby function to reduce the power consumption by the system. The standby
function is available in the two modes: the STOP mode and HALT mode.
Differences between these two modes are as follows:
(1) STOP mode
In the STOP mode, the main system clock oscillator is stopped, and the entire system stops. The current
used by the CPU is reduced to quite a low level.
In addition, the contents of data memory can be preserved with a low supply voltage of down to V
DD
=
1.8V, that is, this mode is effective to retain data memory with a very low current.
The STOP mode of the µPD750008 can be released by an interrupt request to enable intermittent
operations. However, when the STOP mode is released, a wait time is needed for stable oscillation. Select
the HALT mode when processing must be started immediately after an interrupt request.
(2) HALT mode
In the HALT mode, the CPU clock is stopped, but the oscillation of the system clock oscillator continues.
In this mode, the system uses more current than in the STOP mode. However, the HALT mode is suitable
for starting processing immediately after an interrupt request or for intermittent operations such as watch
operation.
In either mode, all contents of the registers, flags, and data memory that are present immediately before
the standby mode is set are preserved. In addition, the states of the output latches of the I/O ports and the
states of the output buffers are also preserved, so that the states of the I/O ports are to be processed to minimize
the power consumption of the entire system.
Cautions 1. The STOP mode can be used only for the main system clock. (Subsystem clock
generation cannot be terminated.) The HALT mode can be used for either the main
system clock or the subsystem clock.
2. If the STOP mode is set when main system clock f
X
is used for clock timer operation,
the clock stops operating. For continued operation, the clock must be changed to
subsystem clock f
XT
before the STOP mode is set.
3. A lower power consumption and lower-voltage operation are enabled by switching
standby modes or switching CPU and system clocks. However, a switching time as
described in Section 5.2.3 is required before operation is started with a new clock after
the clock is selected with the control register. For this reason, when the clock
switching function is used together with a standby mode, the standby mode must be
set after a time needed for switching elapses.
4. Configure I/O ports for minimum power consumption in the stand by mode. Be sure
to connect signals which are high or low to input ports.
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