NEC PD750008 - Manual (Page 169)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(6) Error detection
In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded
into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the
methods described below.
(a) Comparing SIO data before start of transmission with SIO data after start of transmission
With this method, the occurrence of a transmission error is assumed when two SIO values disagree
with each other.
(b) Using the slave address register (SVA)
Transmit data is set in SVA as well before the data is transmitted. On completion of transmission,
the COI bit (match signal from the address comparator) of serial operation mode register (CSIM) is
tested. If the result is 1, the transmission is regarded as successful. If the result is 0, the occurrence
of a transmission error is assumed.
(7) Application of two-wire serial I/O mode
A serial bus is configured, and multiple devices are connected to it.
Example A system is configured with a µPD750008 as the master to which a µPD75104, µPD75402A,
and µPD7225G are connected as slaves.
To configure the bus as shown above, connect the SI pin and SO pin. Then, writes FFH to the shift register
to make the SO pin high except when serial data is output, and free the bus by setting off the output buffer.
The SO pin of the µPD75402A cannot go into a high-impedance state, so that a transistor must be
connected as shown in the figure to make open collector output appear on the pin. When data is input,
00H must be set beforehand in the shift register to set the transistor off.
The timing of data output by each microcomputer must be predetermined.
Port
µPD750008 (master)
SO/SB0
CS
SI
µPD7225G
V
DD
SCK SCK
SCK
SO
µPD75402A
SI
SCK
SO
µPD75104
SI