NEC PD750008 - Manual (Page 85)

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CHAPTER 4 INTERNAL CPU FUNCTIONS
When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting
of the RBS.
A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program
memory address 0.
When a vectored interrupt occurs, the RBE is automatically set to the state of bit 6 in the vector address
table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is
used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.
4.9 BANK SELECT REGISTER (BS)
The bank select register (BS) consists of a register bank select register (RBS) and memory bank select
register (MBS), which specify a register bank and memory bank to be used, respectively.
The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively.
The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the
PUSH BS/POP BS instruction.
Figure 4-17. Bank Select Register Format
(1) Memory bank select register (MBS)
The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data
memory address. The contents of this register specify a memory bank to be accessed. The µPD750008
allows memory banks 0, 1, and 15 only to be specified.
The MBS is set with the SEL MBn instruction (n = 0, 1, 15).
Figure 3-2 shows the range of addressing using MBE and MBS settings.
A RESET signal initializes the MBS to 0.
(2) Register bank select register (RBS)
The register bank select register specifies a register bank to be used as general registers; a register bank
can be selected from register banks 0 to 3.
The RBS is set by the SEL RBn instruction (n = 0 to 3).
A RESET signal initializes the RBS to 0.
Symbol
BS MBS3 MBS2 MBS1 MBS0 0 0 RBS1 RBS0
F83H F82H
Address
F82H