NEC PD750008 - Manual (Page 155)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(a) Slave address detection
[In the SBI mode]
SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8-
bit register for a slave to set its slave address (number assigned to it). The master outputs a slave
address to the connected slaves to select a particular slave. Two data values (a slave address output
from the master and the value of SVA) are compared with each other by the address comparator. If
a match is found, the slave is selected.
At this time, bit 6 (COI) of serial operation mode register (CSIM) is set to 1.
If a match with received address data is not found, the bus release detection flag (RELD) is cleared
to 0. When WUP = 1 (wake-up state detection), IRQCSI is set only when a match is found. With this
interrupt request, the µPD750008 can be informed of a communication request transmitted from the
master.
(b) Error detection
[In the two-wire serial I/O mode or SBI mode]
SVA detects an error when addresses, commands, or data is transferred with the µPD750008
operating as the master or when data is transferred with the µPD750008 operating as a slave. (For
details, see (6) in Section 5.6.6 and (8) in Section 5.6.7.)
5.6.4 Operation Halt Mode
The operation halt mode is used when serial transfer is not performed. This mode reduces power
consumption.
The shift register does not perform shift operation in this mode, so the shift register can be used as a normal
8-bit register.
When the RESET signal is entered, the operation halt mode is set. The P02/SO/SB0 pin and P03/SI/SBI
pin function as input-only port pins. The P01/SCK pin can be used as an input port pin by setting the serial
operation mode register.
(1) Register setting
To set the operation halt mode, manipulate serial operation mode register (CSIM). (For details on CSIM
format, see (1) in Section 5.6.3.)
CSIM is manipulated with an 8-bit manipulation instruction. Only the CSIE bit of CSIM can be
independently manipulated. CSIM can also be manipulated using the name of each bit.
When the RESET signal is entered, CSIM is set to 00H.
In the figure below, hatched portions indicate bits used in the operation halt mode.