NEC PD750008 - Manual (Page 177)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Serial interface operation enable/disable specification bit (W)
Shift register operation Serial clock counter IRQCSI flag SO/SB0 and SI/SB1 pins
CSIE 1 Shift operation enabled Count operation Can be set Used in each mode
as well as for port 0
Signal from address comparator (R)
COI Note Condition for being cleared (COI = 0) Condition for being set (COI = 1)
When the slave address register (SVA) When the slave address register (SVA)
does not match the data of the shift register matches the data of the shift register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An
undefined value may be read during transfer.
COI data written by an 8-bit manipulation instruction is ignored.
Wake-up function specification bit (W)
WUP 0 Sets IRQCSI each time serial transfer is completed in each mode.
1 Used in the SBI mode only to set IRQCSI only when an address received after bus release
matches the data in the slave address register (wake-up state). SB0 or SB1 goes to high-
impedance state.
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode,
the BUSY signal is output until the next falling edge of the serial clock (SCK) appears after
release of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or
SB1) pin is high after releasing BUSY.
Serial interface operation mode selection bit (W)
CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function
0 1 0 SIO
7-0
<—> XA SB0/P02 (N-ch P03 input
(Transfer starting with MSB) open-drain I/O)
1 P02 input SB1/P03 (N-ch
open-drain I/O)