NEC PD750008 - Manual (Page 160)

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µPD750008 USER'S MANUAL
SCK
SI
IRQCSI
1
SO
2 3 4 5 6 7 8
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
Transfer operation is started in phase with falling edge of SCK.
Execution of instruction that writes data to SIO (Transfer start request)
Completion of transfer
Figure 5-44. Timing of Three-Wire Serial I/O Mode
The SO pin becomes a CMOS output and outputs the state of the SO latch. So the output state of the
SO pin can be manipulated by setting the RELT bit and CMDT bit.
However, this manipulation must not be performed during serial transfer.
The output level of the SCK pin can be controlled by manipulating the P01 output latch in the output mode
(internal system clock mode). (See Section 5.6.8.)
(3) Serial clock selection
To select the serial clock, manipulate bits 0 and 1 of serial operation mode register 0 (CSIM). The serial
clock can be selected out of the following four clocks:
Table 5-7. Serial Clock Selection and Application (In the Three-Wire Serial I/O Mode)
Mode register Serial clock
Timing for shift register R/W and
Application CSIM CSIM
Source
Masking of
start of serial transfer
1 0 serial clock
0 0 External Automatically <1> In the operation halt mode Slave CPU
SCK masked when (CSIE = 0)
0 1 TOUT
8-bit data <2> When the serial clock is
Half-duplex asyn
flip-flop
transfer is masked after 8-bit transfer
chronous transfer
completed <3> When SCK is high
(software control)
1 0 f
X
/2 4 Middle-speed
serial transfer
1 1 f
X
/2 3 High-speed serial
transfer