NEC PD750008 User Manual
Page 115
95
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
(2) Procedure for changing the system clock and CPU clock
The procedure for changing the system clock and CPU clock is explained using Figure 5-19.
Figure 5-19. Changing the System Clock and CPU Clock
<1>
A RESET signal starts CPU operation at the lowest speed of the main system clock (10.7 µs at
6.00 MHz,15.3 µs at 4.19 MHz) after a wait time
Note 1
for stable oscillation.
<2>
The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the
voltage on the V
DD
pin to be high enough for highest-speed operation.
<3>
The removal of commercial current is detected using, for example, an interrupt input
Note 2
, then bit
0 of the SCC is set to 1 to operate with the subsystem clock. (In this case, subsystem clock
generation must have been started.) After a time (46 machine cycles) required to switch to the
subsystem clock elapses, bit 3 of the SCC is set to 1 to terminate main system clock generation.
<4>
After detecting the input of commercial current by using an interrupt, bit 3 of the SCC is cleared
to start main system clock generation. After a time required for stable generation, bit 0 of the SCC
is cleared to 0 to operate at the highest speed.
Notes 1. The following two wait times can be selected by a mask option:
2
17
/f
X
(21.8ms at 6.00 MHz, 31.3ms at 4.19 MHz)
2
15
/f
X
(5.46ms at 6.00 MHz, 7.81ms at 4.19 MHz)
However, the µPD75P0016 does not have a mask option and its wait time is fixed to 2
15
/f
X.
2. INT4 is useful.
ON
OFF
Commercial
power
line voltage
V
DD
pin voltage
RESET signal
System clock
CPU clock
Wait
Note 1
f
X
= 6.00 MHz
f
XT
= 32.768 kHz
f
X
10.7 µs
f
X
0.67 µs
f
XT
122 µs
f
X
0.67 µs
Internal reset
operation