NEC PD750008 - Manual (Page 152)

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µPD750008 USER'S MANUAL
Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3)
Busy enable bit (R/W)
BSYE 0 <1> The busy signal is automatically disabled.
<2> Busy signal output is stopped in phase with the falling edge of SCK immediately after
clear instruction execution.
1 The busy signal is output after the acknowledge signal in phase with the falling edge of SCK.
Acknowledge detection flag (R)
ACKD Condition for being cleared (ACKD = 0) Condition for being set (ACKD = 1)
<1> The transfer operation is started. The acknowledge signal (ACK) is detected
<2> The RESET signal is generated. (in phase with the rising edge of SCK).
Acknowledge enable bit (R/W)
ACKE 0 Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)
1 When set before transfer ACK is output in phase with the 9th clock of SCK.
When set after transfer ACK is output in phase with SCK immediately following
the set instruction execution.
Acknowledge trigger bit (W)
ACKT When set after transfer, ACK is output in phase with the next SCK. After ACK signal output,
this bit is automatically cleared to 0.
Cautions 1. Never set ACKT before or during serial transfer.
2. ACKT cannot be cleared by software.
3. Before setting ACKT, set ACKE = 0.
Command detection flag (R)
CMDD Condition for being cleared (CMDD = 0) Condition for being set (CMDD = 1)
<1> The transfer start instruction is executed. The command signal (CMD) is detected.
<2> The bus release signal (REL)
<3> The RESET signal is generated.
<4> CSIE = 0 (Figure 5-40)