Functions and operations of the clock generator – NEC PD750008 User Manual

Page 105

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.2.2 Functions and Operations of the Clock Generator

The clock generator generates the following clocks, and controls the CPU operation modes such as the

standby mode.

• Main system clock f

X

• Subsystem clock f

XT

• CPU clock

F

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC) and system

clock control register (SCC). The function and operation of the clock generator are described in (a) to (g) below.

(a) A RESET signal selects the lowest-speed mode (10.7 µs at 6.00 MHz)

Note 1

for the main system clock

(PCC = 0, SCC = 0).

(b) When the main system clock is selected, the PCC can be set to select one of four CPU clocks (0.67

µs, 1.33 µs, 2.67 µs, and 10.7 µs at 6.00 MHz)

Note 2

.

(c) When the main system clock is selected, the two standby modes, STOP mode and HALT mode, are

available.

(d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122 µs

at 32.768 kHz). The value in the PCC does not affect the CPU clock.

(e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC.

In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock

generation cannot be stopped.)

(f) The clock to be supplied to peripheral hardware is produced by frequency-dividing the main system

clock signal. The subsystem clock can directly be supplied only to the clock timer. This enables the

clock function and the buzzer output function to continue operating even in the standby state.

(g) When the subsystem clock is selected, the clock timer can continue to operate normally. The serial

interface, timer/event counter, and timer counter can continue to operate when the external clock is

selected. However, other hardware cannot be used when the main system clock is stopped because

they operate with the main system clock.

Notes 1. At f

X

= 4.19 MHz: 15.3 µs

2. At f

X

= 4.19 MHz: 0.95 µs, 1.91 µs, 3.81 µs, and 15.3 µs

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